1. Field of the Invention
The invention relates to a manufacturing method of semiconductor device having a vertical transistor.
2. Brief Description of Related Technology
Recently, in semiconductor devices like Dynamic random access memory (DRAM), technology capable of increasing the integration density of semiconductor devices by forming more transistors in a restricted area is required. For this, vertical transistor technology is suggested.
Vertical transistor technology has come into the spot light as a transistor of choice for various devices as well as for DRAM since it can use a restricted area more efficiently by using a vertical channel.
A vertical transistor can be a very efficient means for short channel effect (SCE) since it can maintain a fixed channel length regardless of the reduction of the area of element. Particularly, the surrounding gate can maximize the gate controllability to improve the SCE, while providing excellent operating current characteristics since the area where the current flows is large.
However, when the surrounding gate of the vertical transistor is formed, the pillar can fall down due to a high aspect ratio.
FIGS. 1a to 1e are cross sectional views showing a typical method of manufacturing semiconductor devices having a vertical transistor.
Referring to FIG. 1a, a hard mask pattern 15 defining the pillar region is formed on a semiconductor substrate 10, while the semiconductor substrate 10 is etched using the hard mask pattern 15 as an etch mask, such that an upper portion of pillar 20 is formed.
Referring to FIG. 1b, an oxide layer 30 for forming a spacer is formed on the resultant structure of FIG. 1a. 
Referring to FIG. 1c, a spacer 35 is formed by performing an etch back process on the resultant structure of FIG. 1b, and a lower portion of pillar 40 connected with the upper portion of pillar 20 is formed by etching the semiconductor substrate 10 using the spacer 35 as an etch mask.
Referring to FIG. 1d, a channel region 45 is formed by performing an isotropic etching on the side wall of the lower portion of pillar 40 using the spacer 35 as an etch barrier.
Referring to FIG. 1e, after a gate material 50 is formed on the resultant structure of FIG. 1d, and the gate material 50 is dry etched using the hard mask pattern 15 and the upper portion of pillar 20 as an etch mask, so that a surrounding gate which surrounds the channel region 45 is formed.
In the meantime, when the channel region 45 is formed, the pillar is susceptible to falling down since the channel region 45 is slimmer than the upper portion of pillar 20. In addition, when the etch process for the gate material is not performed, a short circuit phenomenon has been found to occur often between the surrounding gates.